Semiconductor manufacturing method using a high extinction coefficient dielectric photomask

ABSTRACT

A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer. In one embodiment, an etch-stop layer is deposited on a semiconductor substrate, a dielectric layer is deposited on top of the etch-stop layer, and a BARC is deposited on top of the dielectric layer. The BARC is deposited by PECVD to enrich the BARC with semiconductor material to increase the extinction coefficient of the BARC so its thickness can be reduced. A photoresist layer with a thickness less than the thickness of the BARC is then deposited on top of the BARC. The photoresist is then patterned, photolithographically processed, developed, and removed. The BARC is then etched away in the pattern developed on the photoresist and the photoresist is then removed. The BARC is then used as a mask for the etching of the dielectric layer. A conductive material is deposited over the BARC and the dielectric layer and is subsequently removed in the process of polishing the conductive material without requiring a separate BARC removal step.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application contains subject matter related to aconcurrently filed U.S. Patent Application by Ramkumar Subramanian,Wenge Yang, Marina V. Plat, and Lewis Shen entitled “SEMICONDUCTORMANUFACTURING METHOD USING A DIELECTRIC PHOTOMASK”. The relatedapplication is assigned to Advanced Micro Devices, Inc and is identifiedby Ser. No. 09/586,556.

The present application also contains subject matter related to aconcurrently filed U.S. Patent Application by Ramkumar Subramanian, MinhVan Ngo, Suzette K. Pangrle, Kashmir S. Sahota, and Christopher F. Lyonsentitled “METHOD FOR CREATING PARTIALLY UV TRANSPARENT ANTI-REFLECTIVECOATING FOR SEMICONDUCTORS”. The related application is assigned toAdvanced Micro Devices, Inc and is identified by Ser. No. 09/588,119.

The present application also contains subject matter related to aconcurrently filed U.S. Patent Application by Ramkumar Subramanian, MinhVan Ngo, Kashmir S. Sahoto, YongZhong Hu, Hiroyuki Kinshita, Fei Wangand Wenge Yang entitled “METHOD FOR USING A LOW DIELECTRIC CONSTANTLAYER AS A SEMICONDUCTOR ANTI-REFLECTIVE COATING”. The relatedapplication is assigned to Advanced Micro Devices, Inc and is identifiedby Ser. No. 09/586,264.

The present application also contains subject matter related to aconcurrently filed U.S. Patent Application by Kashmir S. Sahota,YongZhong Hu, Hiroyuki Kinoshita, Minh Van Ngo, Ramkumar Subramanian,Fei Wang, and Wenge Yang entitled “METHOD FOR ELIMINATINGANTI-REFLECTIVE COATING FOR SEMICONDUCTORS”. The related application isassigned to Advanced Micro Devices, Inc and is identified by Ser. No.09/588,117.

TECHNICAL FIELD

The present invention relates generally to manufacturing semiconductorsand more particularly to patterning semiconductors using masks.

BACKGROUND ART

Flash electrically erasable programmable read only memories (FlashEEPROMs) are a class of nonvolatile memory devices that are programmedby hot electron injection and erased by Fowler-Nordheim tunneling.

In the first step of putting such electrical devices on a semiconductor,each memory cell is formed on a semiconductor substrate (i.e., a silicondie or chip), having a heavily doped drain region and a source regionembedded therein. The source region further contains a lightly dopeddeeply diffused region and a more heavily doped shallow diffused regionembedded into the substrate. A channel region separates the drain regionand the source region. The memory cell further includes a multi-layerstructure, commonly referred to as a “stacked gate” structure or wordline. The stacked gate structure typically includes: a thin gatedielectric or tunnel oxide layer formed on the surface of substrateoverlying the channel region; a polysilicon floating gate overlying thetunnel oxide; an interpoly dielectric layer overlying the floating gate;and a polysilicon control gate overlying the interpoly dielectric layer.Additional layers, such as a silicide layer (disposed on the controlgate), a poly cap layer (disposed on the silicide layer), and a siliconoxynitride layer (disposed on the poly cap layer) may be formed over thecontrol gate. A plurality of Flash EEPROM cells may be formed on asingle substrate.

After the formation of the memory cells, electrical connections, asecond step of forming what is commonly known as “contacts” must occurto connect the stack gated structure, the source region and the drainregions to other part of the chip. The contact process starts with theformation of sidewall spacers around the stacked gate structures of eachmemory cell. An etch-stop layer, typically a nitride material suchsilicon nitride, is then formed over the entire substrate, including thestacked gate structure, using conventional techniques, such as chemicalvapor deposition (CVD). A dielectric layer, generally of oxide, is thendeposited over the nitride layer. A layer of photoresist is then placedover the dielectric layer and is photolithographically patterned,exposed, and developed (“processed”) to form the pattern of contactopenings. An anisotropic etch is then used to etch out portions of thedielectric layer to form source and drain contact openings. The contactopenings stop at the source and drain regions in the substrate. Thephotoresist is then stripped, and a conductive material, such astungsten, is deposited over the dielectric layer and fills the sourceand drain contact openings to form so-called “self-aligned contacts”(conductive contacts). The substrate is then subjected to achemical-mechanical polishing (CMP) process, which removes theconductive material above the dielectric layer to form the conductivecontacts through a contact CMP process.

Subsequent steps involving a “damascene” process are used to form localinterconnects between the various conductive contacts. An etch-stoplayer is formed over the CMP processed surface and a layer ofphotoresist is then placed over the etch-stop layer and isphotolithographically processed to form the pattern of contact openings.Next, a dielectric layer, generally of oxide, is then deposited and alayer of photoresist is then placed over the dielectric layer and isphotolithographically processed to form the pattern of first level localinterconnect channel openings. An anisotropic etch is then used to etchout portions of the dielectric layer to form the channel openings. Thechannel openings stop at the etch-stop layer except at the contactopenings. The photoresist is then stripped, and a conductive material,such as aluminum or copper, is deposited over the dielectric layer andfills the channel openings. A CMP process removes the conductivematerial above the dielectric layer to form the local interconnects, or“wires”.

Additional levels of local interconnect and vias connecting theadditional levels of local interconnect are formed in “dual damascene”processes which are substantially the same as described above with theexception that certain etching steps and conductive material fillingsteps are combined.

The use of photolithography and photoresist is common to each of thesevarious processes. As semiconductor devices have shrunk in size, theindustry has turned towards deep ultraviolet (DUV) lithography as aphotolithographic exposure process to pattern openings in sub-0.35micron line geometry semiconductor devices.

A major obstacle to the miniaturization of semiconductors is the effectof reflectivity in the DUV lithographic and conventional i-linelithographic processes. Reflections occur at the junctions of materialsand are influenced in part by the thickness of materials. Because theprecision of the photolithographic process is sensitive to suchreflections, reducing the reflections by lowering the reflectivity ofmaterials with good control across wafers and within wafers to underabout 15% is essential. In particular, the differences in thicknesscaused by the polysilicon, metal, and poly/metal stacks has made smallfeature patterning and critical dimension (CD) control of photoresistvery difficult. Such topography causes unpredictable swings in materialreflectivity and needs to be reduced or dampened in some way in order toreduce semiconductor device size. Non-uniformities occurring when thedielectric layer undergoes CMP can increase the total reflectivity fromthe dielectric to the photoresist during photolithography and causefurther disruptions in patterning.

To solve the problem posed by reflectivity, different anti-reflectivecoatings (ARCs) have been developed which work by phase shiftcancellation of specific wavelengths to provide uniform photoresistpatterning. These ARCs are specifically designed so that the reflectivelight from the photoresist/ARC interface is equal in amplitude butopposite in phase to the light reflected from the ARC/reflective layerinterface.

It has been found that there are certain line width variations which aredue to the ARC not being able to reduce the reflective layerreflectivity to a minimum. The reflectivity causes problems with thephotoresist which have been corrected in part by the use of bottomanti-reflective coatings (BARCs) under the photoresists.

Silicon oxynitride (SiON) by itself has been found to be a good BARCmaterial. In essence, the silicon oxynitride BARC serves two functionsduring semiconductor memory manufacturing: (1) as a hard mask duringself-aligned etch (SAE) and during self-aligned-source etch; and (2) asa bottom anti-reflective layer for photolithography at second gatemasking.

However, the variations in small feature patterning and CD control havenot been eliminated through the use of a SiON BARC.

It appears that during the etching process to etch the SiON not coveredby photoresist, variations in the photoresist prevent full etching fromoccurring and the resulting variation in the SiON is greater than thevariation in the photoresist. When subsequent etching occurs with theSiON used as a mask layer, these variations are once again passed downand magnified.

One solution involved compensating for the problem and insuring that thesize of the openings at the bottom of the etched region was the correctsize. This was accomplished by over-sizing the size of thephotolithographic pattern openings. Unfortunately, this results inlarger feature sizes, and therefore slower and less efficientsemiconductor devices.

In addition, the presence of a BARC typically requires a removal stepafter it has served its purpose. Because each additional step greatlyincreases the complexity and speed with which a semiconductor device canbe created, the use of a BARC has significant disadvantages.

A method of minimizing the variation in the etching process to allow forsmaller semiconductor devices without increasing the number ofproduction steps has long been sought, but has eluded those skilled inthe art.

DISCLOSURE OF THE INVENTION

The present invention provides a method of manufacturing a semiconductorwith minimized variation in the etching process by using SiON as abottom antireflective (BARC) layer and hard mask in conjunction with athin photoresist layer.

The present invention further provides a method of manufacturing asemiconductor with minimized variation in the etching process.Patterning is improved by the use of SiON as a BARC. The thinphotoresist layer allows for less variation in the photolithographicprocess. As a result, there is significantly less variation in the SiONand in turn, there is significantly less variation in later layers inwhich SiON is used as a hard mask.

The present invention further provides a method of manufacturing asemiconductor without a separate step for BARC removal. Afterphotolithography, a pattern is etched into the BARC. The BARC is thenused as a hard mask making the photoresist unnecessary. By the sametoken, when the dielectric layer is etched, the BARC is no longerrequired as a hard mask. Because of the thinness of the photoresist,both the photoresist and the BARC layer are removed as by-products ofsubsequent etching steps once they are no longer required, thereforeeliminating the need for a separate step to remove the remaining BARCmaterial. If the BARC material is not removed during the etching steps,it can be removed during the chemical-mechanical polishing process.

The present invention further provides a method of manufacturing asemiconductor with minimized variation in the etching process andwithout a separate step for BARC removal. An etch-stop layer isdeposited on a semiconductor substrate, a dielectric layer is depositedon top of the etch-stop layer, a BARC is deposed on top of thedielectric layer, and a photoresist layer with a thickness less than thethickness of the dielectric layer is then deposited on top of the BARC.The photoresist is then patterned, photolithographically processed, anddeveloped. The BARC is then etched into the pattern developed on thephotoresist. The etched BARC is then used as a hard mask for thepatterned etching of the dielectric layer. As a by-product of this etch,the photoresist is removed. The dielectric layer is then used as a maskfor the etching of the etch-stop layer. As a by-product of this etch,the BARC is removed.

The present invention further provides a method of manufacturing asemiconductor with minimized variation in the etching process andwithout a separate step for BARC removal. A nitride etch-stop layer isdeposited on a silicon substrate, a layer of silicon oxide is depositedon top of the nitride etch-stop layer, a silicon oxynitride layer isdeposited on top of the silicon oxide layer, and a photoresist layerwith a thickness less than the thickness of the silicon oxide layer isthen deposited on top of the silicon oxynitride layer. The photoresistis then patterned, photolithographically processed, and developed. Thesilicon oxynitride layer is then etched into the pattern developed onthe photoresist. The etched silicon oxynitride layer is then used as ahard mask for the patterned etching of the silicon oxide layer. As aby-product of this etch, the photoresist is removed. The silicon oxidelayer is then used as a mask for the etching of the nitride etch-stoplayer. As a by-product of this etch or a subsequent chemical-mechanicalpolish, the silicon oxynitride layer is removed.

The above and additional advantages of the present invention will becomeapparent to those skilled in the art from a reading of the followingdetailed description when taken in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (PRIOR ART) is a plan view of a conventional memory device;

FIG. 2A (PRIOR ART) is schematic diagram of a portion of a memory cellarray;

FIG. 2B (PRIOR ART) is a plan view of a portion of an intermediate state(partially complete) of a memory cell array core;

FIG. 2C (PRIOR ART) is a simplified cross section of FIG. 2B (PRIOR ART)along line 2C—2C;

FIG. 2D (PRIOR ART) is a simplified cross section of FIG. 2B (PRIOR ART)along line 2D—2D;

FIGS. 3A (PRIOR ART) through 3H (PRIOR ART) illustrate a partialsequence of process steps of a conventional process for forming aninterconnect structure and its associate contact on a semiconductorsubstrate, and

FIGS. 4A through 4G illustrate the sequence of process steps of aprocess in accordance with the present invention for forming aninterconnect structure and its associate contact on a semiconductorsubstrate including the use of SiON as a bottom anti-reflective layer inconjunction with a thin photoresist layer.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring now to FIG. 1 (PRIOR ART), therein is shown a plan view of aconventional memory device, a Flash EEPROM 100 which commonly includes asilicon semiconductor substrate 102 in which one or more high-densitycore regions and one or more low-density peripheral portions are formed.High-density core regions typically include one or more M×N array cores104 of individually addressable, substantially identical memory cells200. Low-density peripheral portions 106 typically include input/output(I/O) circuitry and circuitry for selectively addressing the individualmemory cells. The selective addressing circuitry typically includes oneor more x-decoders and y-decoders, cooperating with the I/O circuitryfor connecting the source, gate, and drain of selected addressed memorycells to predetermined voltages or impedances, to effect designatedoperations on the memory cell, e.g., programming, reading and erasing,and deriving necessary voltages to effect such operations.

Referring now to FIG. 2A (PRIOR ART), therein is shown a schematicdiagram of a portion of a memory cell array in which each memory cell200 in array core 104 typically comprises a source 202, a drain 204, anda channel 206 (shown in FIG. 2C (PRIOR ART)).

Referring now to FIG. 2B (PRIOR ART), therein is shown a plan view of aportion of an intermediate state (partially complete) of a memory cellarray core 104.

Referring now to FIG. 2C (PRIOR ART), therein is shown a simplifiedcross section of FIG. 2B (PRIOR ART) along line 2C—2C. The source 202,drain 204, and channel 206 semiconductor regions are shown formed insemiconductor substrate 102 (or in an isolation well) and multi-layerstructures, commonly referred to as “stacked gate” (word line)structures 210. The stacked gate structures 210 include: a thin gatedielectric layer 212 (commonly referred to as the “tunnel oxide”) formedon the surface of substrate 102 overlying the channel 206, a floatinggate 214 overlying the gate dielectric layer 212, an interpoly(inter-gate) dielectric layer 216 overlying the floating gate 214, and acontrol gate 218 overlying the interpoly dielectric layer 216.Additional layers, such as a silicide layer 224 (disposed on the controlgate 218), a poly cap layer 226 (disposed on the silicide layer 224),and a SiON layer 228 (disposed on the poly cap layer 226) may be formedover the control gate 218. The memory cells 200 are arranged in a seriesof rows and columns.

In the completed array, the control gates 218 of the memory cells 200 ina row are formed integral to a common word line (WL) associated with therow. Columns of memory cells are arranged such that adjacent memorycells in a column share a common semiconductor region as a source ordrain region. The source 202 of each memory cell in a column (except endmemory cells) is formed in a common region with one of the adjacentmemory cells, e.g., the preceding memory cell in the column. Likewise,the drain of the memory cell is formed in a common region with the drain204 of the other adjacent memory cell, e.g., the next succeeding memorycell in the column (except end memory cells). The drain 204 of eachmemory cell in a column of memory cells is connected by a conductive bitline (BL) (FIG. 2A (PRIOR ART)), including an overlying layer of metalconnected to each drain 204 of the memory cells 200 within the column.Additionally, the sources 202 of each memory cell 200 in a row (andhence pairs of rows) are interconnected by a common source line CS(FIGS. 2A (PRIOR ART)), which are formed in the substrate 102, as willbe described. Any particular memory cell 200 within the array cores 104can be individually addressed (programmed and read) by operating uponone word line and one bit line.

Typically, in forming an EEPROM 100, a pattern of field oxide regions220 (FIG. 2B (PRIOR ART)) is initially formed to provide electricalisolation between the respective devices of EEPROM 100. For example,field oxide regions 220 are used to provide isolation between the arraycores 104 and the devices of peripheral portions 106, as well as betweenthe various columns of memory cells 200 within the array cores 104.Field oxide regions 220 are conventionally formed using a mask andselective growth process: a layer of thermal oxide (“barrier oxide” or“pad oxide”) is grown or deposited over the surface of the substrate102; a mask, frequently composed of nitride, is deposited on the barrieroxide, and patterned to cover those regions of the substrate 102 inwhich devices are to be formed (herein referred to as active regions);field oxide is grown in the exposed areas of the barrier oxide, by forexample, the local oxidation of silicon (LOCOS); and the masking layerand barrier oxide are stripped to expose the underlying substrate 102.In general, referring to FIG. 2B (PRIOR ART), within the array cores104, the selective growth process results in alternating parallel stripsof field oxide regions 220 and exposed regions corresponding to thecolumns of memory cells 200 in the array.

The stacked gate (word line) structures 210 are then typically formed.For example, gate dielectric layer 212, comprising a thin (e.g.approximately 100 A) layer of oxide, is initially formed on thesubstrate 102 by a technique, such as thermal oxidation of the surfaceof the substrate 102 or by depositing a suitable material on thesubstrate 102. A layer of conductive polysilicon (e.g., polycrystallinesilicon), that will ultimately form the floating gates 214, is typicallythen formed on the gate dielectric layer 212. For example, conductivepolysilicon may be deposited by a number of different techniques, e.g.,furnace-grown polysilicon. The polysilicon layer is typically thenmasked and etched to remove strips overlying the field oxide regions220, leaving isolated strips of polysilicon on top of the gatedielectric layer 212 overlying the substrate regions corresponding tothe columns of memory cells 200 of the array core 104 (i.e. the regionsin which source, channel, and drain regions of memory cells in thecolumn will be formed). A layer of dielectric material, such as, e.g.,an oxide-nitride-oxide (ONO) layer, that will ultimately form interpolydielectric layer 216 is typically then formed by a suitable technique.For example, where the interpoly dielectric layer 216 is ONO, it isformed by growing a layer of oxide, depositing a layer of nitride,followed by growing another layer of oxide. The interpoly dielectriclayer 216, in the completed array, insulates control gates 218 fromfloating gates 214 in the individual memory cells and electricallyisolates the adjacent columns of the floating gates 214 in the arraycore 104. Another layer of conductive polysilicon (e.g., polycrystallinesilicon), that will ultimately form the control gates 218 and the wordlines WL connecting the control gates 218 of the memory cells in therespective rows of the array core 104, referred to as the control gate218, is typically then thermally grown on the interpoly dielectric layer216. Portions of the control gate 218 and the interpoly dielectric layer216 are typically then selectively removed to define the stacked gatestructures 210 on the gate dielectric layer 212, i.e., to form thefloating gates 214, the interpoly dielectric layer 216, control gates218 of the individual memory cells, and the word lines WL (portions ofthe interpoly dielectric layer 216 and control gate polysilicon layerbridge field oxide regions 220 to connect the respective memory cells ofthe rows of the core array). This is typically effected by masking andetching techniques.

When completed, this etch creates the generally parallel, stacked gate(word line) structures 210 separated by a distance D_(WL), as shown inFIG. 2C (PRIOR ART). A silicide layer 224 is typically provided over thecontrol gate 218 layer to reduce resistance. Thereafter, a polysiliconlayer (commonly referred to as a “poly cap” layer) 226 is formed overthe silicide layer 224 to serve as a cap layer for the stacked gatestructures 210. Next, the SiON layer 228 may be formed over the poly caplayer 226. The combination of the poly cap layer 226 and the SiON layer228 is commonly referred to as a “passivation layer”. Thereafter,portions of the SiON layer 228 are partially removed using conventionalmasking and etching techniques to define the final stacked gatestructures 210.

Conventionally, the portions of the field oxide regions 220 and the gatedielectric layer 212 between every second pair of adjacent stacked gate(word line) structures 210 in the array core 104 (i.e., the regions,generally indicated as 222, where the sources 202 are to be formed andthe portions of the field oxide regions 220 disposed between sources 202of the corresponding memory cells of adjacent columns) are thentypically removed in preparation for formation of the common line CS(not shown) connecting the sources 202. This is typically effected usinga conventional Self-Aligned Source (SAS) etch.

Referring now to FIG. 2D (PRIOR ART), therein are shown the source 202,common line CS, and drain 204 regions formed in a conventional process.The source 202 and the common source line CS are typically formed byinitially effecting a conventional double diffusion implant (DDI) withthe SAS mask still in place. The DDI implants a first dopant (e.g.n-type, such as phosphorous) to form a deeply diffused, but lightlydoped, N well ²⁰²L establishing a graded source-channel junction asshown in FIG. 2D (PRIOR ART) which is a simplified cross section of FIG.2B (PRIOR ART) along line 2D—2D. The SAS mask is then removed. The DDIimplant is typically driven deeper into the substrate 102 by subjectingthe substrate 102 to a thermal cycle at high temperature (e.g. 1050°Celsius). A shallow second implant, commonly referred to as a mediumdiffused drain (MDD) implant, is then performed (e.g., with arsenic) tocreate a more heavily doped, but shallower, n+ well 202 _(H) embeddedwithin deep N well 202 _(L). The MDD implant also forms a shallow,abrupt drain 204.

Referring now to FIG. 3A (PRIOR ART), therein is shown a cross-sectionof a simplified semiconductor 300 in an intermediate stage ofprocessing. At this stage are shown a P-type doped semiconductorsubstrate 302 with a N-channel transistor 304, an active region 305, andshallow trench isolations (STI) 306 and 308. Included in the transistor304 are a polysilicon gate 310, a source region 312, and a drain region314. Another polysilicon gate 316 is shown disposed atop STI 308. TheSTI 306 electrically isolates N-channel transistor 304 and the activeregion 305. Similarly, the STI 308 electrically isolates the activeregion 305 and the polysilicon gate 316. In a typical process to formcontacts and interconnect structures, a contact will be formed on thedrain region 314, a Local Interconnect (LI) will be formed between theactive region 305 and the polysilicon gate 316, and, although not shown,another contact will be formed on the LI. For purposes of illustration,transistor 304 and active region 305 represent elements of a logicdevice, while the polysilicon gate 316 represents an element of a memorydevice.

Also shown on the device are a nitride-based LI etch stop layer 318deposited over the entire surface of the semiconductor substrate 302, adielectric layer 320, such as an oxide, deposited over the etch-stoplayer 318 and having subsequently undergone chemical-mechanicalpolishing (CMP) to planarize the surface, a bottom anti-reflectivecoating (BARC) 322 deposited over the surface of the dielectric layer320 after planarization, and a photoresist layer 324 spun on top of thedielectric layer 320.

Referring now to FIG. 3B (PRIOR ART), therein is shown the patterning ofthe photoresist layer 324, which acts as an LI mask pattern. Due to thethickness of the photoresist layer 324, the photolithographic processproduces variations 326 in the spaces in the photoresist pattern.

Referring now to FIG. 3C (PRIOR ART), therein is shown the etching ofcontact opening 328 and LI opening 330 in the BARC 322 following the LImask pattern of photoresist layer 324. The BARC 322 now acts as a hardmask. The variations 326 in the photoresist layer 324 extend to the BARC322 during the etching process.

Referring now to FIG. 3D (PRIOR ART), therein is shown the deepening ofthe contact opening 328 and the LI opening 330 in the dielectric layer320 by using the BARC 322 as a hard mask in conjunction with aconventional dielectric etch technique. The etchstop layer 318 stops theetching process. Part of the photoresist layer 324 is removed in theetching process. The variations 326 in the photoresist layer 324 and theBARC 322 extend to the dielectric layer 320 during the etching process.

Referring now to FIG. 3E (PRIOR ART), therein is shown the deepening ofthe contact opening 328 and the LI opening 330 by removing the exposedetch-stop layer 318 using a conventional nitride etch technique. Most ofthe photoresist layer 324 is removed in this etching process. Thevariations 326 due to the thickness of the photoresist layer 324 extendto the etch-stop layer 318 during the etching process.

Referring now to FIG. 3F (PRIOR ART), therein is shown deposition of aconductive material 332, such as tungsten or aluminum although coppercan also be used. The conductive material fills the contact opening 328and the LI opening 330.

Referring now to FIG. 3G (PRIOR ART), therein is shown the structure ofFIG. 3F (PRIOR ART) after CMP to form a contact 334 and a LI channel336. While some of the BARC 322 is removed, if it is of SiON, it is timeconsuming to CMP large thicknesses.

Referring now to FIG. 3H (PRIOR ART), therein is shown the removal ofthe BARC 322 in a separate etching step. Since the etching step isselective for the BARC 322, the conductive material of the contact 334and LI channel 336 will extend above the dielectric layer 320, which isnot etched.

Referring now to FIG. 4A, therein is shown a cross-section of asimplified semiconductor 400 in an intermediate stage of processing. Atthis stage, the semiconductor is identical to that of FIG. 3A (PRIORART) and depicts a P-type doped semiconductor substrate 402 with aN-channel transistor 404, an active region 405, and shallow trenchisolations (STI) 406 and 408. Included in the transistor 404 are apolysilicon gate 410, a source region 412, and a drain region 414.Another polysilicon gate 416 is shown disposed atop STI 408. STI 406electrically isolates N-channel transistor 404 and the active region405. Similarly, STI 408 electrically isolates the active region 405 andthe polysilicon gate 416. In a typical process to form contacts andinterconnect structures, a contact will be formed on the drain region414, a Local Interconnect (LI) will be formed between the active region405 and the polysilicon gate 416, and, although not shown, anothercontact will be formed on the LI. For purposes of illustration,transistor 404 and active region 405 represent elements of a logicdevice, while polysilicon gate 416 represents an element of a memorydevice. The method of the present invention is not limited in scope tothe example illustrated here and can apply to any semiconductor devicesusing similar processes.

Also shown on the device are a nitride-based LI etch stop layer 418deposited over the entire surface of the semiconductor substrate 402, adielectric layer 420, such as a silicon oxide, deposited over theetch-stop layer 418 and having subsequently undergonechemical-mechanical polishing (CMP) to planarize the surface, a bottomanti-reflective coating (BARC) 422 deposited over the surface of theplanarized dielectric layer 420, and a thin photoresist layer 424 spunon top of the dielectric layer 420. The BARC 422 can be a siliconoxynitride (SiON), which is rich in silicon in order to increase itsextinction coefficient over the conventional silicon oxynitride used inBARC, which is in the range of K=−0.4 to −0.5.

In the present invention, a plasma enhanced chemical vapor deposition(PECVD) process is used to deposit the SiON. In order to increase thesilicon concentration in the SiON, as contrasted to a conventional PECVDprocess, the SiH₄ flow can be increased, the N₂O flow decreased, theradio frequency power decreased, and/or the pressure decreased. Thesilicon is increased in order to increase the extinction coefficient tobe what is defined as a “high” extinction coefficient of above K=−1.1,and preferably around K=−1.3, selected for the particular wavelength oflight which is to be used during the photolithographic process appliedto the thin photoresist layer 424. The extinction coefficient is too“high” when the SiON starts to reflect light.

By increasing the extinction coefficient, it is possible to reduce thethickness of the BARC while maintaining the same reflectivity. In thebest mode, the SiON can be made less than 400 Å in thickness and bepreferably in the 300 to 400 Å range.

Referring now to FIG. 4B, therein is shown the thin photoresist layer424 after undergoing photolithography and developing the thinphotoresist layer 424 to form a contact and LI mask pattern. Due to thethinness of the thin photoresist layer 424, which is thinner than theBARC 422, any variation in the thin photoresist layer 424 will beminimized.

Referring now to FIG. 4C, therein is shown the etching of contactopening 428 and LI opening 430 in the BARC 422 following the LI maskpattern of the thin photoresist layer 424. The BARC 422 now acts as ahard mask. Because of thinness of the thin photoresist layer 424, it isalmost entirely removed as a result of the etching process.

Referring now to FIG. 4D, therein is shown the deepening of the contactopening 428 and the LI opening 430 in the dielectric layer 420 by usingthe BARC 422 as a hard mask in conjunction with a conventionaldielectric etch technique. The etch-stop layer 418 stops the etchingprocess. The remainder of the thin photoresist layer 424 is removed aswell as a portion of the BARC 422 as a result of the etching process.

Referring now to FIG. 4E, therein is shown the deepening of the contactopening 428 and the LI opening 430 by removing the exposed etch-stoplayer 418 using a conventional etch technique, such as a nitride etch.

Referring now to FIG. 4F, therein is shown the deposition of conductivematerial 432 which conformally fills the contact opening 428 and the LIopening 430.

Referring now to FIG. 4G, therein is shown contact 434 and LI channel436, which are formed after conductive material CMP. Since the BARC 422is comparatively thin, the conductive material CMP also removes the BARC422 without requiring a further second dielectric etch.

While the invention has been described in conjunction with a specificbest mode, it is to be understood that many alternatives, modifications,and variations will be apparent to those skilled in the art in light ofthe foregoing description. Accordingly, it is intended to embrace allsuch alternatives, modifications, and variations which fall within thespirit and scope of the included claims. All matters set forth herein orshown in the accompanying drawings are to be interpreted in anillustrative and non-limiting sense.

The invention claimed is:
 1. A method of manufacturing a semiconductorcomprising the steps of: providing a substrate of a semiconductormaterial; depositing an etch-stop layer on the semiconductor substrate;depositing a first dielectric layer on the etch-stop layer; depositing asecond dielectric layer on top of the first dielectric layer, the seconddielectric layer enriched with semiconductor material to increase theextinction coefficient thereof; depositing a photoresist on the seconddielectric layer; patterning the photoresist; photolithographicallyprocessing the photoresist at the processing wavelength; developing thephotoresist; etching the second dielectric layer using the developedphotoresist; etching the first dielectric layer using the seconddielectric layer; etching the etch-stop layer using the seconddielectric layer whereby the photoresist is also etched away; depositingconductive material over the second and the first dielectric layers; andremoving the conductive material and the second dielectric layer down tothe first dielectric layer.
 2. The method for manufacturing asemiconductor as claimed in claim 1 wherein the extinction coefficientof the second dielectric layer is a high extinction coefficient selectedfor the wavelength of light used for photolithographically processingthe photoresist.
 3. The method for manufacturing a semiconductor asclaimed in claim 1 wherein the step of depositing the second dielectriclayer deposits a second dielectric layer having a thickness less thanthe thickness of the first dielectric layer.
 4. The method formanufacturing a semiconductor as claimed in claim I wherein the step ofdepositing the second dielectric layer deposits a second dielectriclayer having a thickness below 400 Å.
 5. The method of manufacturing asemiconductor as claimed in claim 1 wherein the step of depositing thesecond dielectric layer deposits a second dielectric layer having athickness of between 300 to 400 Å.
 6. The method of manufacturing asemiconductor as claimed in claim 1 wherein the step of depositing thesecond dielectric layer deposits the second dielectric layer usingplasma enhanced chemical vapor deposition.
 7. The method ofmanufacturing a semiconductor as claimed in claim 1 wherein the step ofdepositing the second dielectric layer deposits the second dielectriclayer using plasma enhanced chemical vapor deposition modified to enrichthe second dielectric layer with the same material as the semiconductorsubstrate.
 8. A method of manufacturing a semiconductor comprising thesteps of: providing a silicon substrate; providing a plurality ofsemiconductor devices on and in the silicon substrate; depositing anitride over the plurality of semiconductor devices; depositing siliconoxide on the nitride layer; depositing silicon oxynitride on the siliconoxide, the silicon oxynitride enriched with silicon to increase theextinction coefficient thereof; depositing a photoresist on the siliconoxynitride; patterning the photoresist with a pattern of openings;photolithographically processing the photoresist; developing thephotoresist; etching the silicon oxynitride in the pattern of openingsusing the developed photoresist as a mask; etching the silicon oxide inthe pattern of openings using the silicon oxynitride as a mask wherebythe photoresist is also etched away; depositing conductive material overthe silicon oxynitride and the silicon oxide; and removing theconductive material and the silicon oxynitride down to the siliconoxide.
 9. The method for manufacturing a semiconductor as claimed inclaim 8 wherein the extinction coefficient of the silicon oxynitride isgreater than 2.0 for the wavelength of light used forphotolithographically processing the photoresist and the thickness ofthe silicon oxynitride is less than 400 Å.
 10. The method formanufacturing a semiconductor as claimed in claim 8 wherein theextinction coefficient of the silicon oxynitride is greater than K=−1.1for the wavelength of light used for photolithographically processingthe photoresist and the thickness of the silicon oxynitride is between300 to 400 Å.
 11. The method for manufacturing a semiconductor asclaimed in claim 8 wherein the step of depositing the silicon oxynitridedeposits a silicon oxynitride having a thickness less than the thicknessof the silicon oxide.
 12. The method of manufacturing a semiconductor asclaimed in claim 8 wherein the step of depositing the silicon oxynitridedeposits a silicon oxynitride between 300 to 400 Å thick.
 13. The methodof manufacturing a semiconductor as claimed in claim 8 wherein the stepof depositing the silicon oxynitride deposits the silicon oxynitrideusing plasma enhanced chemical vapor deposition.
 14. The method ofmanufacturing a semiconductor as claimed in claim 8 wherein the step ofdepositing the silicon oxynitride deposits the silicon oxynitride usingplasma enhanced chemical vapor deposition modified to enrich the siliconoxynitride with silicon.